Fully encrypted high-speed microprocessor architecture: The secret computer in simulation

Journal article


Breuer, PT and Bowen, JP (2019). Fully encrypted high-speed microprocessor architecture: The secret computer in simulation. International Journal of Critical Computer-Based Systems. 9 (1-2), pp. 26-55.
AuthorsBreuer, PT and Bowen, JP
Abstract

Copyright © 2019 Inderscience Enterprises Ltd. The architecture of an encrypted high-performance microprocessor designed on the principle that a nonstandard arithmetic generates encrypted processor states is described here. Data in registers, in memory and on buses exists in encrypted form. Any block encryption is feasible, in principle. The processor is (initially) intended for cloud-based remote computation. An encrypted version of the standard OpenRISC instruction set is understood by the processor. It is proved here, for programs written in a minimal subset of instructions, that the platform is secure against ‘Iago’ attacks by the privileged operator or a subverted operating system, which cannot decrypt the program output, nor change the program’s output to a particular value of their choosing. Performance measures from cycle-accurate behavioural simulation of the platform are given for 64-bit RC2 (symmetric, keyed) and 72-bit Paillier (asymmetric, additively homomorphic, no key in-processor) encryptions. Measurements are centred on a nominal 1 GHz clock with 3 ns cache and 15 ns memory latency, which is conservative with respect to available technology.

Year2019
JournalInternational Journal of Critical Computer-Based Systems
Journal citation9 (1-2), pp. 26-55
ISSN1757-8779
Digital Object Identifier (DOI)doi:10.1504/IJCCBS.2019.098797
Publication dates
Print19 Mar 2019
Publication process dates
Deposited23 Apr 2019
Accepted01 Jan 2019
Accepted author manuscript
License
CC BY 4.0
Permalink -

https://openresearch.lsbu.ac.uk/item/86733

  • 6
    total views
  • 15
    total downloads
  • 0
    views this month
  • 6
    downloads this month

Related outputs

The Secret Processor Will Go to the Ball: Benchmark Insider-Proof Encrypted Computing.
Breuer, PT, Bowen, JP, Palomar, E and Liu, Z (2018). The Secret Processor Will Go to the Ball: Benchmark Insider-Proof Encrypted Computing. 2018 IEEE European Symposium on Security and Privacy Workshops. 23 - 27 Apr 2018 IEEE. pp. 145-152 doi:10.1109/EuroSPW.2018.00027
Encrypted computing: Speed, security and provable obfuscation against insiders
Breuer, PT, Bowen, JP, Palomar, E and Liu, Z (2017). Encrypted computing: Speed, security and provable obfuscation against insiders. International Carnahan Conference on Security Technology. Madrid, Spain 23 - 26 Oct 2017 London South Bank University. doi:10.1109/CCST.2017.8167847
On obfuscating compilation for encrypted computing
Breuer, PT, Bowen, JP, Palomar, E and Liu, Z (2017). On obfuscating compilation for encrypted computing. 14th International Conference on Security and Cryptography. Madrid, Spain 24 - 26 Jul 2017 London South Bank University.
A practical encrypted microprocessor
Breuer, PT, Bowen, JP, Palomar, E and Liu, Z (2016). A practical encrypted microprocessor. IEEE Proceedings of the 13th International Joint Conference on e-Business and Telecommunications. Lisbon, Portugal 26 - 28 Jul 2016 London South Bank University. doi:10.5220/0005955902390250
A Fully Encrypted Microprocessor: The Secret Computer is Nearly Here
Breuer, PT and Bowen, JP (2016). A Fully Encrypted Microprocessor: The Secret Computer is Nearly Here. Procedia Computer Science. 83, pp. 1282-1287.
An Open Question on the Uniqueness of (Encrypted) Arithmetic
Breuer, PT and Bowen, JP (2013). An Open Question on the Uniqueness of (Encrypted) Arithmetic. International Conference on Computational Science. Barcelona, Spain 05 - 07 Jun 2013 London South Bank University.
Empirical Patterns in Google Scholar Citation Counts
Breuer, PT and Bowen, JP (2014). Empirical Patterns in Google Scholar Citation Counts. 2014 IEEE 8th International Symposium on Service Oriented System Engineering. 07 - 11 Apr 2014 IEEE. doi:10.1109/SOSE.2014.55
Certifying Machine Code Safe from Hardware Aliasing: RISC is not necessarily risky
Breuer, PT and Bowen, JP (2013). Certifying Machine Code Safe from Hardware Aliasing: RISC is not necessarily risky. International Conference on Software Engineering and Formal Methods. Madrid, Spain London South Bank University. doi:10.1007/978-3-319-05032-4_27
On the Security of Fully Homomorphic Encryption and Encrypted Computing: Is Division safe?
Breuer, PT and Bowen, JP (2014). On the Security of Fully Homomorphic Encryption and Encrypted Computing: Is Division safe? arXiv.