Fully encrypted high-speed microprocessor architecture: The secret computer in simulation
Breuer, PT and Bowen, JP (2019). Fully encrypted high-speed microprocessor architecture: The secret computer in simulation. International Journal of Critical Computer-Based Systems. 9 (1-2), pp. 26-55.
|Authors||Breuer, PT and Bowen, JP|
Copyright © 2019 Inderscience Enterprises Ltd. The architecture of an encrypted high-performance microprocessor designed on the principle that a nonstandard arithmetic generates encrypted processor states is described here. Data in registers, in memory and on buses exists in encrypted form. Any block encryption is feasible, in principle. The processor is (initially) intended for cloud-based remote computation. An encrypted version of the standard OpenRISC instruction set is understood by the processor. It is proved here, for programs written in a minimal subset of instructions, that the platform is secure against ‘Iago’ attacks by the privileged operator or a subverted operating system, which cannot decrypt the program output, nor change the program’s output to a particular value of their choosing. Performance measures from cycle-accurate behavioural simulation of the platform are given for 64-bit RC2 (symmetric, keyed) and 72-bit Paillier (asymmetric, additively homomorphic, no key in-processor) encryptions. Measurements are centred on a nominal 1 GHz clock with 3 ns cache and 15 ns memory latency, which is conservative with respect to available technology.
|Journal||International Journal of Critical Computer-Based Systems|
|Journal citation||9 (1-2), pp. 26-55|
|Digital Object Identifier (DOI)||doi:10.1504/IJCCBS.2019.098797|
|19 Mar 2019|
|Publication process dates|
|Deposited||23 Apr 2019|
|Accepted||01 Jan 2019|
|Accepted author manuscript|
CC BY 4.0
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