Pipelined median architecture

Journal article


Cadenas, O (2015). Pipelined median architecture. Electronics Letters. 51 (24), pp. 1999-2001.
AuthorsCadenas, O
Abstract

The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four-step procedure method to compute the running median of the last N W-bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B-bit using a pipeline of W/B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N, W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared to latest methods in the literature.

KeywordsMedian; Pipelined designs; 0906 Electrical And Electronic Engineering; 0801 Artificial Intelligence And Image Processing; 1005 Communications Technologies; Electrical & Electronic Engineering
Year2015
JournalElectronics Letters
Journal citation51 (24), pp. 1999-2001
PublisherInstitute of Electrical Engineers
ISSN0013-5194
Digital Object Identifier (DOI)doi:10.1049/el.2015.1898
Publication dates
Print19 Nov 2015
Publication process dates
Deposited09 May 2017
Accepted02 Oct 2015
Accepted author manuscript
License
CC BY 4.0
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https://openresearch.lsbu.ac.uk/item/8759q

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