Pipelined median architecture
Cadenas, O (2015). Pipelined median architecture. Electronics Letters. 51 (24), pp. 1999-2001.
The core processing step of the noise reduction median filter technique is to find the median within a window of integers. A four-step procedure method to compute the running median of the last N W-bit stream of integers showing area and time benefits is proposed. The method slices integers into groups of B-bit using a pipeline of W/B blocks. From the method, an architecture is developed giving a designer the flexibility to exchange area gains for faster frequency of operation, or vice versa, by adjusting N, W and B parameter values. Gains in area of around 40%, or in frequency of operation of around 20%, are clearly observed by FPGA circuit implementations compared to latest methods in the literature.
|Keywords||Median; Pipelined designs; 0906 Electrical And Electronic Engineering; 0801 Artificial Intelligence And Image Processing; 1005 Communications Technologies; Electrical & Electronic Engineering|
|Journal citation||51 (24), pp. 1999-2001|
|Publisher||Institute of Electrical Engineers|
|Digital Object Identifier (DOI)||doi:10.1049/el.2015.1898|
|19 Nov 2015|
|Publication process dates|
|Deposited||09 May 2017|
|Accepted||02 Oct 2015|
|Accepted author manuscript|
CC BY 4.0
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