A Hardware-Based Acquisition Engine For GNSS Receivers

The undergoing modernisation of global navigation satellite system (GNSS) has resulted in development of new navigation signals with longer spreading codes and new techniques
to improve signal power and better multipath mitigation, such as binary offset carrier (BOC), this will improve the pseudorange calculation and enables more robust navigation.
On the other side, this development requires receivers capable to process these new signals to deliver accurate positioning, navigation, and timing (PNT) solutions. To achieve this, the satellite acquisition process has to be improved to acquire the modernised signal in an efficient way. The double-block zero padding (DBZP) algorithm is commonly used for acquiring and detecting weak GNSS signals. It improves the acquisition method by reducing the number of operations in the block correlation used to determine the Doppler frequency and time of the received signal. However, 50% of the power consumption and time during the partial correlation process is lost because of performing correlation on doubled blocks (two periods) and maintaining the output from only the first block.
This work presents an innovative modelling method for the development of an efficient and stand-alone core based on the DBZP methodology in a field programmable gate array (FPGA) for the acquisition of GNSS signals. The main core consists of two components. The first component performs a partial correlation on the incoming signal without double blocking the incoming signal and zero padding the replica code. The second component performs discrete Fourier transform (DFT) on the output of the partial correlation results obtained from the first component. The core is designed without using any third-party fast Fourier transform (FFT) intellectual property (IP) cores, digital signal processor (DSP) blocks, or multipliers.
Performing partial correlation on the incoming signal without forming double blocks of the incoming signal and zero padding the replica code limits the computation burden and complexity, thus leading to a substantial improvement in the efficiency of the acquisition process in the hardware based GNSS receiver. The feasibility and performance of the proposed approach are investigated by developing a structural test bench containing the main core under test and a stimulus generator, simulated in ModelSim and the developed system is validated using real recorded Galileo E1 signal in FPGA.